Variations of SNMs in Sub-threshold Circuits

Sub-threshold operation offers a compelling solution for ultra-low energy applications such as micro-sensors and embedded medical applications, where low energy needs are the primary concern instead of speed. By lowering the supply voltage below the transistors’ threshold voltage, we see a dramatic drop in energy consumption when compared to normal operations, but circuit instability and delay variability are increased in subthreshold operation. We must stabilize and mitigate the sensitivity to variation for optimal operation. This project explored variability metrics and noise sensitivity of cascaded logic gates. With the help of HSPICE, an analog circuit simulator, we were able to conduct DC analysis of circuits. We were then able to calculate the SNM, static noise margin, of two cascaded logic gates; this in-turn was used to study the robustness of a circuit at reduced supply voltages through Monte